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S-100 Bus Signal Usage

The following table lists the pin definitions for the IMSAI version of the S-100 bus, including the second-generation with the Intelligent Memory Manager (IMM), and the final IEEE 696 standard.

Over time, IMSAI boards will be added to this list.

PinIMSAI NameIMSAI Gen 2IEEE NameIEEE UsageIEEE Active LevelIMSAI CP-A Rev-4IMSAI DIOIMSAI PDSIMSAI PDS IIIMSAI MPU-AIMSAI MPU-BIMSAI PIC-8IMSAI PIO 4IMSAI RAM 4AIMSAI RAM-16/32/65IMSAI RAM IIIIMSAI SIO 2IMSAI VIO
1 +8V+8V+8 VBX, 33µFX, 33µFX, 33µFX, 2.2µFX, 33µFX, 2.2µFX, 33µFX, 33µFX, 3×33µFX, 33µFX, 2.2µFX, 33µFX, 2.2µF
2 +16V+16V+16 VBX, 33µFX, 2.2µFX, 33µFX, 2.2µFX, 33µFX, 2.2µFX, 33µFX, 2.2µF
3 XRDYXRDYXRDYSHOut, −0.4/16mAIn LS, 1k PU
4 VI0/VI0VI0*SL, OCIn LS, 1kPU
Out OC 8mA		In -250µA,
Out, 1k PU†		Out −1/15mAOut OC (2N3904)Out −0.4/16mA†
5 VI1/VI1VI1*SL, OCIn LS, 1kPU
Out OC 8mA		In -250µA,
Out, 1k PU†		Out −1/15mAOut OC (2N3904)Out −0.4/16mA†
6 VI2/VI2VI2*SL, OCIn LS, 1kPU
Out OC 8mA		In -250µA,
Out, 1k PU†		Out −1/15mAOut OC (2N3904)Out −0.4/16mA†
7 VI3/VI3VI3*SL, OCIn LS, 1kPU
Out OC 8mA		In -250µA,
Out, 1k PU†		Out −1/15mAOut OC (2N3904)Out −0.4/16mA†
8 VI4/VI4VI4*SL, OCIn LS, 1kPU
Out OC 8mA		In -250µA,
Out, 1k PU†		Out −1/15mAOut OC (2N3904)Out −0.4/16mA†
9 VI5/VI5VI5*SL, OCIn LS, 1kPU
Out OC 8mA		In -250µA,
Out, 1k PU†		Out −1/15mAOut OC (2N3904)Out −0.4/16mA†
10 VI6/VI6VI6*SL, OCIn LS, 1kPU
Out OC 8mA		In -250µA,
Out, 1k PU†		Out −1/15mAOut OC (2N3904)Out −0.4/16mA†
PinIMSAI NameIMSAI Gen 2IEEE NameIEEE UsageIEEE Active LevelIMSAI CP-A Rev-4IMSAI DIOIMSAI PDSIMSAI PDS IIIMSAI MPU-AIMSAI MPU-BIMSAI PIC-8IMSAI PIO 4IMSAI RAM 4AIMSAI RAM-16/32/65IMSAI RAM IIIIMSAI SIO 2IMSAI VIO
11 VI7/VI7VI7*SL, OCIn LS, 1kPU
Out OC 8mA		In -250µA,
Out, 1k PU†		Out −1/15mAOut OC (2N3904)Out −0.4/16mA†
12 XRDY2NMI*SL, OCIn LS, 1k PU†
13 AA14PWRFAIL*BLIn LS††In LSIn LS†In LS†
14 AA15TMA3*ML, OCIn LS††In LSIn LS†In LS†
15 A18A18MHIn LS†In LSIn 3LSIn LS
16 A16A16MHIn LS,
Out OC 40mA †		†In LS†In 3LS†In LS,
Out OC 40mA†
17 A17A17MHIn LS†In LSIn 3LSIn LS
18 STSDSBL/STSDSBLSDSB*ML, OCIn LS, 1k PUIn LS, 1k PUIn 2LSIn 3LS
19 CCDSBL/CCDSBLCDSB*ML, OCIn LS, 1k PUIn LS, 1k PU
20 UNPROTUNPROT0 VBT5†In LS†
PinIMSAI NameIMSAI Gen 2IEEE NameIEEE UsageIEEE Active LevelIMSAI CP-A Rev-4IMSAI DIOIMSAI PDSIMSAI PDS IIIMSAI MPU-AIMSAI MPU-BIMSAI PIC-8IMSAI PIO 4IMSAI RAM 4AIMSAI RAM-16/32/65IMSAI RAM IIIIMSAI SIO 2IMSAI VIO
21 SS/DIDSBLOut −0.4/16mAIn LS (no PU)In LS, 1k PU
22 ADDR DSBL/ADDR DSBLADSB*ML, OCIn LS, 1k PUIn LS, 1k PU
23 DODSBL/DODSBLDODSB*ML, OCIn LS, 1k PUIn LS, 1k PU
24 ɸ2ɸ2ɸBAIn, 3Out −5.2/48mAOut −5.2/48mAIn LSIn LSIn LS†In LS
25 ɸ1ɸ1pSTVAL*MLOut −5.2/48mAOut −5.2/48mAIn LSIn LSIn LS
26 PHLDAPHLDApHLDAMHIn†Out 3S −5.2/48mA
In LS (no PU)		Out 3S −5.2/48mA
27 PWAITPWAITRFUIn†Out 3S −5.2/48mAOut 3S −5.2/48mAIn LS†In LSIn LS
28 PINTEPINTERFUIn†Out 3S −5.2/48mA1k PU (jumper)In -250µA†
29 A5A5A5MHIn†In 3LS†Out 3S −5.2/48mAOut 3S −1/15mAIn LSIn LSIn†In LSIn LSIn 2LS†In 2LS†
30 A4A4A4MHIn†In 3LS†Out 3S −5.2/48mAOut 3S −1/15mAIn LSIn LSIn†In LSIn LSIn 2LS†In 2LS†
PinIMSAI NameIMSAI Gen 2IEEE NameIEEE UsageIEEE Active LevelIMSAI CP-A Rev-4IMSAI DIOIMSAI PDSIMSAI PDS IIIMSAI MPU-AIMSAI MPU-BIMSAI PIC-8IMSAI PIO 4IMSAI RAM 4AIMSAI RAM-16/32/65IMSAI RAM IIIIMSAI SIO 2IMSAI VIO
31 A3A3A3MHIn†In LS†Out 3S −5.2/48mAOut 3S −1/15mAIn LSIn LSIn†In LSIn LSIn LSIn 2LS†
32 A15A15A15MHIn LS+†In LS†Out 3S −5.2/48mAOut 3S −5.2/48mAIn LSIn 2LSIn LS†In LS†In LSIn 3LS†
33 A12A12A12MHIn LS+†In LSOut 3S −5.2/48mAOut 3S −5.2/48mAIn LSIn 2LSIn LSIn LS†In LSIn 3LS
34 A9A9A9MHIn LS+†In LS†Out 3S −5.2/48mAOut 3S −5.2/48mAIn LSIn LS†In LSIn LSIn LSIn 2LS†
35 DO1DO1DO1 / ED1M / M/SHIn†Out 3S −1/15mA†Out 3S −5.2/48mAIn -250µA†In −1mA†In LS†In SIn LSIn†In†
36 DO0DO0DO0 / ED0M / M/SHIn†Out 3S −1/15mA†Out 3S −5.2/48mAIn -250µA†In −1mA†In LS†In SIn LSIn†In†
37 A10A10A10MHIn LS+†In LS†Out 3S −5.2/48mAOut 3S −5.2/48mAIn LSIn 5LSIn LSIn LSIn LSIn 2LS†
38 DO4DO4DO4 / ED4M / M/SHIn†Out 3S −1/15mA†Out 3S −5.2/48mAIn LSIn −1mA†In LS†In SIn LSIn†In†
39 DO5DO5DO5 / ED5M / M/SHIn, LSIn†Out 3S −1/15mA†Out 3S −5.2/48mAIn LSIn −1mA†In LS†In SIn LSIn†In†
40 DO6DO6DO6 / ED6M / M/SHIn†Out 3S −1/15mA†Out 3S −5.2/48mAIn LSIn −1mA†In LS†In SIn LSIn†In LS†
PinIMSAI NameIMSAI Gen 2IEEE NameIEEE UsageIEEE Active LevelIMSAI CP-A Rev-4IMSAI DIOIMSAI PDSIMSAI PDS IIIMSAI MPU-AIMSAI MPU-BIMSAI PIC-8IMSAI PIO 4IMSAI RAM 4AIMSAI RAM-16/32/65IMSAI RAM IIIIMSAI SIO 2IMSAI VIO
41 DI2DI2DI2 / OD2M / M/SHOut 3S −1/15mAIn, 1k PU†In LSOut 3S −5.2/48mAOut 3S −5.2/48mAOut 3S −2.6/24mAOut 3S −1/15mAOut 3S −5.2/48mA
42 DI3DI3DI3 / OD3M / M/SHOut 3S −1/15mAIn, 1k PU†In LSOut 3S −5.2/48mAOut 3S −5.2/48mAOut 3S −5.2/48mAOut 3S −2.6/24mAOut 3S −1/15mAOut 3S −5.2/48mA
43 DI7DI7DI7 / OD7M / M/SHOut 3S −1/15mAIn, 1k PU†In LSOut 3S −5.2/48mAOut 3S −5.2/48mAOut 3S −2.6/24mAOut 3S −1/15mAOut 3S −5.2/48mA
44 SM1SM1sM1MHIn†Out 3S −5.2/48mAOut 3S −6.5/20mAIn LSIn LS
45 SOUTSOUTsOUTMHIn 1+LS+†In 2LSOut 3S −5.2/48mAOut 3S −6.5/20mAIn 2LSIn LSIn LSIn LSIn LSIn LSIn
46 SINPSINPsINPMHIn LS+†In LSOut 3S −5.2/48mAOut 3S −6.5/20mAIn LSIn LSIn LSIn LSIn LSIn LS
47 SMEMRSMEMRsMEMRMHIn†In LSOut 3S −5.2/48mAOut 3S −6.5/20mAIn LSIn LS+SIn 2LS
48 SHLTASHLTAsHLTAMHIn†Out 3S −5.2/48mAOut 3S −6.5/20mAIn LSIn LS
49 CLK/CLKCLOCKBAIn LSIn LSOut −5.2/48mAOut −5.2/48mAIn LS†
50 GNDGND0 VBXXXXXXXXXXXXX
PinIMSAI NameIMSAI Gen 2IEEE NameIEEE UsageIEEE Active LevelIMSAI CP-A Rev-4IMSAI DIOIMSAI PDSIMSAI PDS IIIMSAI MPU-AIMSAI MPU-BIMSAI PIC-8IMSAI PIO 4IMSAI RAM 4AIMSAI RAM-16/32/65IMSAI RAM IIIIMSAI SIO 2IMSAI VIO
51 +8V+8V+8 VBXXXXXXXXXXXXX
52 −16V−16V−16 VBX, 2.2µFX, 33µFX, 2.2µFX, 33µFX, 2.2µFX, 33µFX, 2.2µF
53 SSW DSB/SSW DSB0 VBOut, −0.4/8mAIn LS (no PU)
54 EXT CLR/EXT CLRSLAVE CLR*BL, OC1k PU†In LS1k PU†In LSIn LSIn LS
55 CH GNDTMA0*ML, OC
56 TMA1*ML, OC
57 TMA2*ML, OC
58 sXTRQ*ML
59 A19MH
60 SIXTN*SL, OC
PinIMSAI NameIMSAI Gen 2IEEE NameIEEE UsageIEEE Active LevelIMSAI CP-A Rev-4IMSAI DIOIMSAI PDSIMSAI PDS IIIMSAI MPU-AIMSAI MPU-BIMSAI PIC-8IMSAI PIO 4IMSAI RAM 4AIMSAI RAM-16/32/65IMSAI RAM IIIIMSAI SIO 2IMSAI VIO
61 A20MH
62 A21MH
63 A22MH
64 A23MH
65 AA13In LS†
66 AA12In LS†
67 A19PHANTOM*M/SL, OCIn LSIn LSIn 3LSIn LS
68 MWRITEMWRITEMWRTBHOut, −5.2/48mAOut 3S −5.2/48mA,
In LS (no PU)		In LSIn 2LSIn LSIn LSIn LS
69 PS/PSRFUOut 3S −5.2/48mAIn LS†In LS†
70 PROTPROT0 VBGNDIn LS
PinIMSAI NameIMSAI Gen 2IEEE NameIEEE UsageIEEE Active LevelIMSAI CP-A Rev-4IMSAI DIOIMSAI PDSIMSAI PDS IIIMSAI MPU-AIMSAI MPU-BIMSAI PIC-8IMSAI PIO 4IMSAI RAM 4AIMSAI RAM-16/32/65IMSAI RAM IIIIMSAI SIO 2IMSAI VIO
71 RUNRUNRFUOut, −5.2/48mAIn LS, 1k PUIn 2LS, 1k PUIn LSIn LS
72 PRDYPRDYRDYSH, OCOut OC 40mAIn LS, 1k PUIn LS, 1k PUOut 3S −5.2/48mAOut 3S −5.2/48mAOut OC 48mAOut OC 40mA
73 PINT/PINTINT*SL, OCIn LS, 1k PUIn LS, 1k PUOutOut OC (2N3904)
74 PHOLD/PHOLDHOLD*ML, OCInIn LS, 1k PU
75 PRESET/PRESETRESET*BL, OCOutIn, 4.7k PU,
33µF PD)		In, 10k PU,
10µF PD)		Out OC (2N3904)†
76 PSYNCPSYNCpSYNCMHIn 2LSOut 3S −5.2/48mAOut 3S −5.2/48mAIn LSIn LSIn LS
77 PWR/PWRpWR*MLIn 1+2LSIn LS†Out 3S −5.2/48mAOut 3S −5.2/48mAIn LSIn LSIn 4LS†In LSIn LSIn LSIn LS
78 PDBINPDBINpDBINMHIn, LSIn 2LSOut 3S −5.2/48mA
In LS (no PU)		Out 3S −5.2/48mAIn LSIn LSIn 2LSIn 2LSIn LSIn LS
79 A0A0A0MHIn†In LS†Out 3S −5.2/48mAOut 3S −1/15mAIn LSIn LSIn†In LSIn LSIn LSIn 2LS†
80 A1A1A1MHIn†In LS†Out 3S −5.2/48mAOut 3S −1/15mAIn LSIn LSIn†In LSIn LSIn LSIn 2LS†
PinIMSAI NameIMSAI Gen 2IEEE NameIEEE UsageIEEE Active LevelIMSAI CP-A Rev-4IMSAI DIOIMSAI PDSIMSAI PDS IIIMSAI MPU-AIMSAI MPU-BIMSAI PIC-8IMSAI PIO 4IMSAI RAM 4AIMSAI RAM-16/32/65IMSAI RAM IIIIMSAI SIO 2IMSAI VIO
81 A2A2A2MHIn†In LS†Out 3S −5.2/48mAOut 3S −1/15mAIn LSIn LSIn†In LSIn LSIn LSIn 2LS†
82 A6A6A6MHIn†In 3LS†Out 3S −5.2/48mAOut 3S −1/15mAIn LSIn LSIn†In LSIn LSIn 2LS†In 2LS†
83 A7A7A7MHIn†In 3LS†Out 3S −5.2/48mAOut 3S −1/15mAIn LSIn LSIn†In LSIn LSIn 2LS†In 2LS†
84 A8A8A8MHIn LS+†In LS†Out 3S −5.2/48mAOut 3S −5.2/48mAIn LSIn LS†In LSIn LSIn LSIn 2LS†
85 A13A13A13MHIn LS+†In LSOut 3S −5.2/48mAOut 3S −5.2/48mAIn LSIn 2LSIn LSIn LS†In LSIn 3LS
86 A14A14A14MHIn LS+†In LS†Out 3S −5.2/48mAOut 3S −5.2/48mAIn LSIn 2LSIn LS†In LS†In LSIn 3LS†
87 A11A11A11MHIn LS+†In 2LSOut 3S −5.2/48mAOut 3S −5.2/48mAIn LSIn 5LSIn LSIn LSIn LSIn LS
88 DO2DO2DO2 / ED2M / M/SHIn†Out 3S −1/15mA†Out 3S −5.2/48mAIn -250µA†In −1mA†In 2LS†In SIn LSIn†In LS†
89 DO3DO3DO3 / ED3M / M/SHIn†Out 3S −1/15mA†Out 3S −5.2/48mAIn -250µA†In −1mA†In 2LS†In SIn LSIn†In LS†
90 DO7DO7DO7 / ED7M / M/SHIn†Out 3S −1/15mA†Out 3S −5.2/48mAIn −1mA†In LS†In SIn LSIn†In LS†
PinIMSAI NameIMSAI Gen 2IEEE NameIEEE UsageIEEE Active LevelIMSAI CP-A Rev-4IMSAI DIOIMSAI PDSIMSAI PDS IIIMSAI MPU-AIMSAI MPU-BIMSAI PIC-8IMSAI PIO 4IMSAI RAM 4AIMSAI RAM-16/32/65IMSAI RAM IIIIMSAI SIO 2IMSAI VIO
91 DI4DI4DI4 / OD4M / M/SHOut 3S −1/15mAIn, 1k PU†In LSOut 3S −5.2/48mAOut 3S −5.2/48mAOut 3S −5.2/48mAOut 3S −2.6/24mAOut 3S −1/15mAOut 3S −5.2/48mA
92 DI5DI5DI5 / OD5M / M/SHOut 3S −1/15mAIn, 1k PU†In LSOut 3S −5.2/48mAOut 3S −5.2/48mAOut 3S −5.2/48mAOut 3S −2.6/24mAOut 3S −1/15mAOut 3S −5.2/48mA
93 DI6DI6DI6 / OD6M / M/SHOut 3S −1/15mAIn, 1k PU†In LSOut 3S −5.2/48mAOut 3S −5.2/48mAOut 3S −2.6/24mAOut 3S −1/15mAOut 3S −5.2/48mA
94 DI1DI1DI1 / OD1M / M/SHOut 3S −1/15mAIn, 1k PU†In LSOut 3S −5.2/48mAOut 3S −5.2/48mAOut 3S −2.6/24mAOut 3S −1/15mAOut 3S −5.2/48mA
95 DI0DI0DI0 / OD0M / M/SHOut 3S −1/15mAIn, 1k PU†In LSOut 3S −5.2/48mAOut 3S −5.2/48mAOut 3S −2.6/24mAOut 3S −1/15mAOut 3S −5.2/48mA
96 SINTASINTAsINTAMHIn†In LSOut 3S −5.2/48mAOut 3S −6.5/20mAIn LSIn LSIn LSIn
97 SWO/SWOsWO*MLIn†Out 3S −5.2/48mAOut 3S −6.5/20mA
98 SSTACKSSTACKERROR*SL, OCIn†Out 3S −5.2/48mAJumper to GND
99 POC/POCPOC*BLIn, 6In LSOut −5.2/48mAOut −5.2/48mAIn LSIn LSIn LSIn LS
100 GNDGND0 VBXXXXXXXXXXXXX

General Notes

IMSAI S-100 Bus (Gen 1)

Bus pin 55 is reserved for the chassis ground, but none of the boards ever connected to it. For example, the SIO 2 has pin connectors for the chassis ground, but the edge connector pin 55 is not connected at all.

IMSAI S-100 Bus (Gen 2)

IMSAI’s second generation lineup (IMM, MPU-B, RAM-16/32/65, RAM-III, DIO, VIO) defined some new bus pins for the extended addressing generated by the IMM board:

  • XRDY2: The MPU-B uses this line instead of XRDY. Not sure why.
  • AA12—AA15: Alternate address line bits 12 through 15 generated the IMM. Memory cards could jumper over to these lines if desired.
  • A16—A19: Extended address lines to address up to 1 MB. Interestingly, all but A19 were adopted verbatim in the IEEE 696 standard.

Active low signals are designated by a leading /SLASH instead of the OVERBAR used previously.

A16 was used as IMSAI’s /PHANTOM signal by default. It functioned like the IEEE 696 PHANTOM* signal, but was on pin 16 instead of pin 67.

IEEE 696 Bus
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