The following table lists the pin definitions for the IMSAI version of the S-100 bus, including the second-generation with the Intelligent Memory Manager (IMM), and the final IEEE 696 standard.

Over time, IMSAI boards will be added to this list.

Pin	IMSAI Name	IMSAI Gen 2	IEEE Name	IEEE Usage	IEEE Active Level	IMSAI CP-A Rev-4	IMSAI MPU-A	IMSAI MPU-B	IMSAI SIO 2
1	+8V	+8V	+8 V	B		X, 33µF	X, 33µF	X, 2.2µF	X, 33µF
2	+16V	+16V	+16 V	B			X, 33µF	X, 2.2µF	X, 33µF
3	XRDY	XRDY	XRDY	S	H	Out, −0.4/16mA	In LS, 1k PU
4	VI0	/VI0	VI0*	S	L, OC			In LS, 1kPU Out OC 8mA	Out −0.4/16mA †
5	VI1	/VI1	VI1*	S	L, OC			In LS, 1kPU Out OC 8mA	Out −0.4/16mA †
6	VI2	/VI2	VI2*	S	L, OC			In LS, 1kPU Out OC 8mA	Out −0.4/16mA †
7	VI3	/VI3	VI3*	S	L, OC			In LS, 1kPU Out OC 8mA	Out −0.4/16mA †
8	VI4	/VI4	VI4*	S	L, OC			In LS, 1kPU Out OC 8mA	Out −0.4/16mA †
9	VI5	/VI5	VI5*	S	L, OC			In LS, 1kPU Out OC 8mA	Out −0.4/16mA †
10	VI6	/VI6	VI6*	S	L, OC			In LS, 1kPU Out OC 8mA	Out −0.4/16mA †
Pin	IMSAI Name	IMSAI Gen 2	IEEE Name	IEEE Usage	IEEE Active Level	IMSAI CP-A Rev-4	IMSAI MPU-A	IMSAI MPU-B	IMSAI SIO 2
11	VI7	/VI7	VI7*	S	L, OC			In LS, 1kPU Out OC 8mA	Out −0.4/16mA †
12		XRDY2	NMI*	S	L, OC			In LS, 1k PU
13		AA14	PWRFAIL*	B	L
14		AA15	TMA3*	M	L, OC
15		A18	A18	M	H
16		A16	A16	M	H
17		A17	A17	M	H
18	STSDSBL	/STSDSBL	SDSB*	M	L, OC		In LS, 1k PU	In LS, 1k PU
19	CCDSBL	/CCDSBL	CDSB*	M	L, OC		In LS, 1k PU	In LS, 1k PU
20	UNPROT	UNPROT	0 V	B		T5 †
Pin	IMSAI Name	IMSAI Gen 2	IEEE Name	IEEE Usage	IEEE Active Level	IMSAI CP-A Rev-4	IMSAI MPU-A	IMSAI MPU-B	IMSAI SIO 2
21	DIDSBL	/DIDSBL				Out −0.4/16mA	In LS (no PU)	In LS, 1k PU
22	ADDR DSBL	/ADDR DSBL	ADSB*	M	L, OC		In LS, 1k PU	In LS, 1k PU
23	DODSBL	/DODSBL	DODSB*	M	L, OC		In LS, 1k PU	In LS, 1k PU
24	ɸ2	ɸ2	ɸ	B	A	In, 3	Out −5.2/48mA	Out −5.2/48mA	In LS †
25	ɸ1	ɸ1	pSTVAL*	M	L		Out −5.2/48mA	Out −5.2/48mA
26	PHLDA	PHLDA	pHLDA	M	H	In †	Out 3S −5.2/48mA, In LS (no PU)	Out 3S −5.2/48mA
27	PWAIT	PWAIT	RFU			In †	Out 3S −5.2/48mA	Out 3S −5.2/48mA
28	PINTE	PINTE	RFU			In †	Out 3S −5.2/48mA	1k PU (jumper)
29	A5	A5	A5	M	H	In †	Out 3S −5.2/48mA	Out 3S −1/15mA	In 2LS †
30	A4	A4	A4	M	H	In †	Out 3S −5.2/48mA	Out 3S −1/15mA	In 2LS †
Pin	IMSAI Name	IMSAI Gen 2	IEEE Name	IEEE Usage	IEEE Active Level	IMSAI CP-A Rev-4	IMSAI MPU-A	IMSAI MPU-B	IMSAI SIO 2
31	A3	A3	A3	M	H	In †	Out 3S −5.2/48mA	Out 3S −1/15mA	In LS
32	A15	A15	A15	M	H	In LS+ †	Out 3S −5.2/48mA	Out 3S −5.2/48mA	In LS
33	A12	A12	A12	M	H	In LS+ †	Out 3S −5.2/48mA	Out 3S −5.2/48mA	In LS
34	A9	A9	A9	M	H	In LS+ †	Out 3S −5.2/48mA	Out 3S −5.2/48mA	In LS
35	DO1	DO1	DO1 / ED1	M / M/S	H		Out 3S −1/15mA	Out 3S −5.2/48mA	In †
36	DO0	DO0	DO0 / ED0	M / M/S	H		Out 3S −1/15mA	Out 3S −5.2/48mA	In †
37	A10	A10	A10	M	H	In LS+ †	Out 3S −5.2/48mA	Out 3S −5.2/48mA	In LS
38	DO4	DO4	DO4 / ED4	M / M/S	H		Out 3S −1/15mA	Out 3S −5.2/48mA	In †
39	DO5	DO5	DO5 / ED5	M / M/S	H	In, LS	Out 3S −1/15mA	Out 3S −5.2/48mA	In †
40	DO6	DO6	DO6 / ED6	M / M/S	H		Out 3S −1/15mA	Out 3S −5.2/48mA	In †
Pin	IMSAI Name	IMSAI Gen 2	IEEE Name	IEEE Usage	IEEE Active Level	IMSAI CP-A Rev-4	IMSAI MPU-A	IMSAI MPU-B	IMSAI SIO 2
41	DI2	DI2	DI2 / OD2	M / M/S	H		In †, 1k PU	In LS	Out 3S −1/15mA
42	DI3	DI3	DI3 / OD3	M / M/S	H		In †, 1k PU	In LS	Out 3S −1/15mA
43	DI7	DI7	DI7 / OD7	M / M/S	H		In †, 1k PU	In LS	Out 3S −1/15mA
44	SM1	SM1	sM1	M	H	In †	Out 3S −5.2/48mA	Out 3S −6.5/20mA
45	SOUT	SOUT	sOUT	M	H	In 1+LS+ †	Out 3S −5.2/48mA	Out 3S −6.5/20mA	In LS
46	SINP	SINP	sINP	M	H	In LS+ †	Out 3S −5.2/48mA	Out 3S −6.5/20mA	In LS
47	SMEMR	SMEMR	sMEMR	M	H	In †	Out 3S −5.2/48mA	Out 3S −6.5/20mA
48	SHLTA	SHLTA	sHLTA	M	H	In †	Out 3S −5.2/48mA	Out 3S −6.5/20mA
49	CLK	/CLK	CLOCK	B	A		Out −5.2/48mA	Out −5.2/48mA	In LS †
50	GND	GND	0 V	B		X	X	X	X
Pin	IMSAI Name	IMSAI Gen 2	IEEE Name	IEEE Usage	IEEE Active Level	IMSAI CP-A Rev-4	IMSAI MPU-A	IMSAI MPU-B	IMSAI SIO 2
51	+8V	+8V	+8 V	B		X	X	X	X
52	−16V	−16V	−16 V	B			X, 33µF	X, 2.2µF	X, 33µF
53	SSW DSB	/SSW DSB	0 V	B		Out, −0.4/8mA	In LS (no PU)
54	EXT CLR	/EXT CLR	SLAVE CLR*	B	L, OC	1k PU †		1k PU †	In LS
55	CH GND		TMA0*	M	L, OC
56			TMA1*	M	L, OC
57			TMA2*	M	L, OC
58			sXTRQ*	M	L
59			A19	M	H
60			SIXTN*	S	L, OC
Pin	IMSAI Name	IMSAI Gen 2	IEEE Name	IEEE Usage	IEEE Active Level	IMSAI CP-A Rev-4	IMSAI MPU-A	IMSAI MPU-B	IMSAI SIO 2
61			A20	M	H
62			A21	M	H
63			A22	M	H
64			A23	M	H
65		AA13
66		AA12
67		A19	PHANTOM*	M/S	L, OC
68	MWRITE	MWRITE	MWRT	B	H	Out, −5.2/48mA		Out 3S −5.2/48mA, In LS (no PU)	In LS
69	PS	/PS	RFU
70	PROT	PROT	0 V	B		GND
Pin	IMSAI Name	IMSAI Gen 2	IEEE Name	IEEE Usage	IEEE Active Level	IMSAI CP-A Rev-4	IMSAI MPU-A	IMSAI MPU-B	IMSAI SIO 2
71	RUN	RUN	RFU			Out, −5.2/48mA	In LS, 1k PU	In 2LS, 1k PU
72	PRDY	PRDY	RDY	S	H, OC		In LS, 1k PU	In LS, 1k PU
73	PINT	/PINT	INT*	S	L, OC		In LS, 1k PU	In LS, 1k PU
74	PHOLD	/PHOLD	HOLD*	M	L, OC		In	In LS, 1k PU
75	PRESET	/PRESET	RESET*	B	L, OC	Out †	In, 4.7k PU, 33µF PD)	In, 10k PU, 10µF PD)
76	PSYNC	PSYNC	pSYNC	M	H	In 2LS	Out 3S −5.2/48mA	Out 3S −5.2/48mA
77	PWR	/PWR	pWR*	M	L	In 1+2LS	Out 3S −5.2/48mA	Out 3S −5.2/48mA	In LS
78	PDBIN	PDBIN	pDBIN	M	H	In, LS	Out 3S −5.2/48mA, In LS (no PU)	Out 3S −5.2/48mA	In LS
79	A0	A0	A0	M	H	In †	Out 3S −5.2/48mA	Out 3S −1/15mA	In LS
80	A1	A1	A1	M	H	In †	Out 3S −5.2/48mA	Out 3S −1/15mA	In LS
Pin	IMSAI Name	IMSAI Gen 2	IEEE Name	IEEE Usage	IEEE Active Level	IMSAI CP-A Rev-4	IMSAI MPU-A	IMSAI MPU-B	IMSAI SIO 2
81	A2	A2	A2	M	H	In †	Out 3S −5.2/48mA	Out 3S −1/15mA	In LS
82	A6	A6	A6	M	H	In †	Out 3S −5.2/48mA	Out 3S −1/15mA	In 2LS †
83	A7	A7	A7	M	H	In †	Out 3S −5.2/48mA	Out 3S −1/15mA	In 2LS †
84	A8	A8	A8	M	H	In LS+ †	Out 3S −5.2/48mA	Out 3S −5.2/48mA	In LS
85	A13	A13	A13	M	H	In LS+ †	Out 3S −5.2/48mA	Out 3S −5.2/48mA	In LS
86	A14	A14	A14	M	H	In LS+ †	Out 3S −5.2/48mA	Out 3S −5.2/48mA	In LS
87	A11	A11	A11	M	H	In LS+ †	Out 3S −5.2/48mA	Out 3S −5.2/48mA	In LS
88	DO2	DO2	DO2 / ED2	M / M/S	H		Out 3S −1/15mA	Out 3S −5.2/48mA	In †
89	DO3	DO3	DO3 / ED3	M / M/S	H		Out 3S −1/15mA	Out 3S −5.2/48mA	In †
90	DO7	DO7	DO7 / ED7	M / M/S	H		Out 3S −1/15mA	Out 3S −5.2/48mA	In †
Pin	IMSAI Name	IMSAI Gen 2	IEEE Name	IEEE Usage	IEEE Active Level	IMSAI CP-A Rev-4	IMSAI MPU-A	IMSAI MPU-B	IMSAI SIO 2
91	DI4	DI4	DI4 / OD4	M / M/S	H		In †, 1k PU	In LS	Out 3S −1/15mA
92	DI5	DI5	DI5 / OD5	M / M/S	H		In †, 1k PU	In LS	Out 3S −1/15mA
93	DI6	DI6	DI6 / OD6	M / M/S	H		In †, 1k PU	In LS	Out 3S −1/15mA
94	DI1	DI1	DI1 / OD1	M / M/S	H		In †, 1k PU	In LS	Out 3S −1/15mA
95	DI0	DI0	DI0 / OD0	M / M/S	H		In †, 1k PU	In LS	Out 3S −1/15mA
96	SINTA	SINTA	sINTA	M	H	In †	Out 3S −5.2/48mA	Out 3S −6.5/20mA
97	SWO	/SWO	sWO*	M	L	In †	Out 3S −5.2/48mA	Out 3S −6.5/20mA
98	SSTACK	SSTACK	ERROR*	S	L, OC	In †	Out 3S −5.2/48mA	Jumper to GND
99	POC	/POC	POC*	B	L	In, 6	Out −5.2/48mA	Out −5.2/48mA	In LS
100	GND	GND	0 V	B		X	X	X	X

General Notes

IMSAI S-100 Bus (Gen 1)

Bus pin 55 is reserved for the chassis ground, but none of the boards ever connected to it. For example, the SIO 2 has pin connectors for the chassis ground, but the edge connector pin 55 is not connected at all.

IMSAI S-100 Bus (Gen 2)

IMSAI’s second generation lineup (IMM, MPU-B, RAM-16/32/65, RAM-III, DIO, VIO) defined some new bus pins for the extended addressing generated by the IMM board:

XRDY2: The MPU-B uses this line instead of XRDY. Not sure why.
AA12—AA15: Alternate address line bits 12 through 15 generated the IMM. Memory cards could jumper over to these lines if desired.
A16—A19: Extended address lines to address up to 1 MB. Interestingly, all but A19 were adopted verbatim in the IEEE 696 standard.

Active low signals are designated by a leading /SLASH instead of the OVERBAR used previously.

A16 was used as IMSAI’s /PHANTOM signal by default. It functioned like the IEEE 696 PHANTOM* signal, but was on pin 16 instead of pin 67.

S-100 Bus Signal Usage

General Notes

IMSAI S-100 Bus (Gen 1)

IMSAI S-100 Bus (Gen 2)

IEEE 696 Bus