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IMSAI Standard Addresses

While most IMSAI boards have jumpers or DIP switches to let users set the base I/O port or memory mapped I/O address, the boards have what are considered to be standard addresses according to IMSAI CP/M, IMDOS, and many utility programs. The following section documents the standard addresses of most every IMSAI card ever made.

Standard Memory Addresses

The IMSAI address space is 1MB, achieved by adding 4 upper address lines to the S-100 bus. The addresses here represent the default memory-mapped addresses and not RAM card addresses. For this reason, addresses are 5 hexadecimal digits with the upper digit separated by a space for readability. A 4-digit address indicates that the address decode does not take the 4 upper address lines into account, and will appear in all 64 kB banks.

Range End Product Can Disable Comments
0000-07FF   MPU-B Control Port bit 6 The MPU-B begins execution of the firmware ROM here and almost immediately jumps to the D800 space after switching out the ROM here. This leaves this address range available for the system.
0000-EFFF   System    
D000-D0FF   MPU-B Control Port bit 7 The MPU-B on-board RAM.
D100-D103   MPU-B Control Port bit 7 The MPU-B Timers.
D104-D7FF   MPU-B Control Port bit 7 Reserved. Do not use.
D800-DFFF   MPU-B Control Port bit 7 The MPU-B firmware which starts at x 0000 and jumps here to complete the initialization.
E000-EFFF   DIO Control Port The DIO firmware exists from E000 through E7FF. Memory-mapped I/O is addressed from E800 through EFFF.
F000-F7FF   VIO No The VIO video refresh memory and command port when jumper M is not installed (default).
F800-FFFF   VIO No The VIO firmware ROM when S1-5 is OFF jumper M is not installed (default).
FE00-FE0F   SIO 2 No Memory-mapped address, primary. The sixteen address offsets correspond to the I/O addresses. The secondary address range is FE10-FE1F, and so on up to the sixteenth board is FEF0-FEFF.
FF00-FF03   PIO 4 No Memory-mapped address, primary. The four address offsets correspond to the I/O addresses. The secondary address range is FE10-FE1F, and so on up to the sixteenth board is FEF0-FEFF.
F F000-F F7FF   VIO No The VIO video refresh memory and command port when jumper M is installed.
F F800-F FFFF   VIO No The VIO firmware ROM when S1-5 is OFF jumper M is installed. This is where the VIO was supposed to go with an IMM installed. To my knowledge, no software was ever released that used the IMM or the VIO this way.

Standard I/O Addresses

It should be noted that many IMSAI boards decode the address lines in a way that is considered to be non-standard in an IEEE 696 system. This behavior was enabled by the fact that the 8080, 8085, and Z80 processors would duplicate the I/O port address on the upper 8 address lines as well as the lower. For example, a reference to port 12 would output the 16-bit address 1212 on the address lines. Some boards such as the IMSAI CP-A would take advantage of this and decode the I/O port using the upper address lines.

Range Port Product Comments
00−0F   SIO 2 The primary address block. The useful addresseses within this block are sparse. The secondary address range is 10-1F, and so on up to the sixteenth board is F0-FF. The ports in this range are offsets within the range.
0-1 Unused.
2 Channel A data.
3 Channel A control (see 8251 datasheet).
4 Channel B data.
5 Channel B control.
6 Do not use. Channel A and channel B data are both enabled onto the bus.
7 Do not use. Channel A and channel B control are both enabled onto the bus.
8 Control byte for channel A and B. Controls CD, CTS, and interrupt enable.
9-F Do not use.
20-2F   SIO 2 The secondary SIO 2 for the alternate SIO printer port on 22/23. See range 00-0F for offsets.
DE-DF DE DIO The primary DIO Disable Control Port. Any value output to this port disables the secondary DIO in the memory address space.
DF DIO The primary DIO Enable Control Port. Any value output to this port enables the secondary DIO in the memory address space.
EE-EF EE DIO The secondary DIO Disable Control Port. Any value output to this port disables the primary DIO in the memory address space.
EF DIO The secondary DIO Enable Control Port. Any value output to this port enables the primary DIO in the memory address space.
F3   MPU-B The MPU-B control port.
F6   LIF The command port for the IFM/LIB board pair PTR-300.
F7   PIC-8 CP/M 1.3 initializes the PIC-8 board but does not use it.
F8-FB 0-3 PIO 4 The primary address block. The secondary address range is 10-1F, and so on up to the sixteenth board is F0-FF. The ports in this range are offsets within the range.
FD   FIF The command port for the IFM/FIB board pair 8" SSSD floppy controller.
FE   RAM-4A Controls the memory protect of each 1 KiB block in a 64 KiB system. See the RAM 4A documentation for details.
FF   CP-A Reads the upper 8 address switches (A15 through A8) into bits 7 through 0; writes to the Programmed Output LEDs.

 


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