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EAD-696 Go back

The EAD-696 is a very small circuit board that adds IEEE 696 extended addressing capabilities to nearly any legacy S-100 board that was designed for 16 or 20 memory address bits and 8 I/O address bits. Its low profile lets you mount it on top of existing ICs and still stay within the IEEE 696 specifications for component height. It is roughly the size of a 40-pin DIP and usually mounts close to the S-100 card edge connector.

The circuit is designed to make it simple to retrofit onto any S-100 board’s address decoder circuit whether it is active-high or active-low. The simplest way to retrofit onto an existing address decoder is to splice the EAD-696 into the circuit. Find the output of the address decoder and the first place the PCB trace takes it. Cut that trace, run a wire from the address decoder to the EAD-696 input, and run another wire from the EAD-696 output to where the address decoder went. Wire up power, ground, and the S-100 address lines. Set the DIP switches for the desired extended address.

Theory of Operation

The circuit is very simple and has only four components: a 74ALS520 8-bit identity comparator, an 8-position DIP switch, a 74LVC2G14 for the two inverters needed to handle active-low and active-high configurations, and a 0.1µF bypass capacitor. The 74ALS520 has integrated 20kΩ pull-up resistors on the Q inputs, eliminating the need for a pull-up resistor network. The eight address DIP switches are connected between the 74ALS520 Q inputs and ground. The eight P inputs are connected to the address input pads 1 through 8. The /(P=Q) output is connected to the OUT-AL pad 17 and to the OUT-AH pad through an inverter. The /G input is connected to the IN-AL pad. The other inverter is available on the INV IN/OUT pads 11/12 to provide an active-high input.

Interface Connections

The EAD-696 has through-hole pads on the top and bottom edges of the board to facilitate wiring and mounting. The power and interface signaling are across the top. The eight address lines are across the bottom. The S-100 bus connector pins you connect to depend on whether you are extending memory or I/O addresses.

Connection Legend Pin Pin Legend Description
(memory) (I/O)
S-100 pin 16. S-100 pin 84. A16/8 1 18 +5V Connect to +5V.
S-100 pin 17. S-100 pin 34. A17/9 2 17 GND Connect to ground.
S-100 pin 15. S-100 pin 37. A18/10 3 16 OUT-AL Active-low output.
S-100 pin 59. S-100 pin 87. A19/11 4 15 OUT-AH Active-high output.
S-100 pin 61. S-100 pin 33. A20/12 5 14 0V
S-100 pin 62. S-100 pin 85. A21/13 6 13 IN-AL Active-low input. Wire to 0V if not used.
S-100 pin 63. S-100 pin 86. A22/14 7 12 INV-OUT Inverter output for active-high decoders. Wire to IN-AL if used.
S-100 pin 64. S-100 pin 32. A23/15 8 11 INV-IN Inverter input for active-high decoders. Wire to 0V if not used.
  0V 9 10 0V

Underlined bus pin numbers are on the bottom (solder) side of the board and will have to be accessed through nearby vias. We recommend insulated 30 AWG wire wrap wire because it will feed through the vias of most old S-100 era boards. It is not recommended to mount the EAD-100 on the bottom side of the board because it would violate the IEEE 696 board clearance specification.

If you have some flexibility in integrating the EAD-696 into your board’s address decoder, using the OUT-AL output and the IN-AL input (if needed) is the lowest-delay configuration at a 20ns at 70°C. Using the OUT-AH or INV-IN each adds a maximum of 4.3ns delay each. See the EAD-696 manual for complete specifications.

If your system only needs 4 address bits, wire the unused ones to GND and make sure DIP switches 4 through 8 are ON.



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