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IMSAI MPU-B

IMSAI MPU-B Rev 2IMSAI MPU-B Rev 1The IMSAI MPU-B is an 8085A processor board with a serial port, bi-directional parallel port, 3 timers, 256 bytes of RAM, and a 2KiB monitor ROM. The 8085A runs at 3 MHz while maintaining similar bus timing of a 2 MHz 8080A due to the improved bus utilization of the 8085A. These onboard peripherals make it possible to build a system without a front panel and an I/O interface card. A RAM and disk controller card are all that is necessary to build a useable system.

There are two MPU-B versions in circulation, Rev 1 and Rev 2. The easiest way to distinguish them is Rev 1 (pictured below) has three TO-220 regulators above the TO-3 regulator in the large heat sink, and is designed for a three-supply EPROM such as the 2708 for the firmware. You are more likely to encounter a Rev 2 MPU-B (pictured above) which has a single-supply 2716 for the firmware. In later builds, a 8316 mask ROM is used which decreases cost and increases reliability (mask ROMs will not fade over decades like EPROMs can).

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We put a lot of time into organizing the information here, especially the DYI resources. If the information here was helpful to you, please consider making a donation to help us continue making content like this available.


IEEE 696 Compliance

The IEE-696 specification did not exist when the MPU-B was designed. These modifications improve its compliance if you plan to use the MPU-B in a more compliant system. These compliance modifications are presented in sections that may be implemented separately or in groups.

You probably do not want to do any of these modifications if the MPU-B is in a system with a CP-A front panel. The CP-A is notoriously non-compliant and needs many of the signals these modifications delete.

XRDY (3), NMI (12)

TODO: introduce this mod.

Cut the trace from J1 (the 100-pin connector) pin 12 at R14. Leave some trace going to pin 12 for later. This releases pin 12 which is NMI under IEEE 696. Tack a “blue wire” from pin 3 to R14 which was cut loose in the previous step. This connects the circuit to the IEEE-696 XRDY signal. If you like, you may tack a jumper from pin 12 to one of the MPU-B’s interrupt pads if you want to use the bus NMI signal. The 8085A does not have a true NMI. Hooking up NMI is completely optional.


Upgrades

We have a few of upgrades here, all designed by Robert Weatherford. These modifications have been verified only on a Rev 2 board. Please consider carefully the impact of any modification you do to your system before proceeding. Consult the schematic and affected component datasheets and make sure you are comfortable with the suggested modifications. Parastream Technologies does not assume responsibility for any impact these modifications will have on your system, good or bad.

For example, before overclocking, make sure your backplane is properly terminated and able to handle the higher frequency signals. Most stock IMSAI backplanes are not up to the task.

Stability

We have seen some problems with oscillation on the −12V rail because it does not have a bypass capacitor near the 7912 output terminal. Install a 1µF 35V solid tantalum capacitor between the outer terminals of the 7912 with the + capacitor lead on the leftmost terminal as you face the 7912 (viewed from the board top or hold the board upside-down).

IMSAI MPU-B 8212 modificationThe lower 8 address lines are latched using an 8212 in U21. The 8212 does not have good bus drive characteristics as it only sinks 15mA and sources -1mA — far less than the 24mA/2mA requirements of IEEE 696. In most stock applications, this seems to work fine, but if the backplane presents a high-current termination load, the 8212 drive may be insufficient. The drive problems may become more problematic if you overclock the board.

One proven way to fix the drive issue is to replace the 8212 with a latch and bus transceiver such as the 74LS373. The photo to the right shows our reference MPU-B with a 24-pin socket header with a 74LS373 tortuously soldered into it to match the 8212 pinout.

A similar issue exists on the status signals. These are generated by a 74S288 PROM in U38. The 74S288 does not have good bus drive characteristics as it only sinks 16mA and sources -1mA — far less than the 24mA/2mA requirements of IEEE 696. TODO: Godbout puts a 'LS244 buffer after the PROM.

Improved IEEE 696 Compliance

/DIDSBL, PWAIT, PINTE
J1 pins 21, 27, and 28 are no longer part of the spec. If no other board in the system uses them, or one or more boards use them for a custom purpose, cut the trace between J1 pins 21, 27, and 28 and their nearest feed-through hole. Deleting “unused” signals from the bus is completely optional.
pSTVAL*
J1 pin 25 is not disabled from the bus when a temporary bus master gets on the bus. If you have older DMA-driven cards such as the IMSAI IFM board, this non-standard behavior needs to be preserved. For this reason, there is not a suggested fix.
ERROR*
J1 pin 98 is now defined as an active-low bus error signal. Cut the trace from J1 pin 98 to 0V.

Operation

When the MPU-B starts up, its monitor firmware is present from address 0x0000 through 0x07FF and 0xD800 through 0xDFFF. It then disables itself in the address range 0x0000 through 0x07FF and jumps to the itself in 0xD800 through 0xDFFF. At this point, the monitor is wating for one of the following to happen:

  • The IFM (if present) reads the boot sector from drive A. If this happens, the boot sector is executed and CP/M or IMDOS is booted.
  • The DIO or MDIO reads the boot sector from drive A. If this happens, the boot sector is executed and CP/M or IMDOS is booted.
  • A character is presented on the control port, MIO, or SIO ports 2 and 3 (see Control Port). The monitor is entered using the control port (see Monitor).

Monitor

The MPU-B monitor can use a VIO board at the default address of 0xF800.

Parallel Port Operation

The monitor will work with the onboard parallel port. The most common use is with an IKB-1 keyboard and a VIO board. Connect a 26-pin DB25 cable to J4 (the left header) and a IKB-1 or other parallel character entry device to the DB-25 connector. DIP Switch SPS (left DIP switch 7) on the MPU-B must be OFF and SPP (left DIP switch 8) must be ON for the monitor to use the onboard parallel port. The system waits for you to press the space bar to enter the monitor.

PARALLEL
IMSAI MPU-B MONITOR    VERS 1.3
?▒

Serial Port Operation

The monitor will work with a serial port. For the SIO, it must be addressed as ports 2 and 3, which is the default, and the baud rate is fixed. DIP Switch SPS (left DIP switch 7) and SPP (left DIP switch 8) on the MPU-B must be OFF for the monitor to use the SIO.

The monitor can use the MPU-B onboard serial port. Connect a 26-pin DB25 cable to J3 (the center header) and a terminal or other DTE equipment to the DB-25 connector. Alternatively, you can connect the cable to J4 (the rightmost header) and a computer or other DCE equipment to the DB-25 connector without having to use a "null modem." DIP Switch SPS (left DIP switch 7) on the MPU-B must be ON and SPP (left DIP switch 8) must be OFF for the monitor to use the onboard serial port. The system waits for you to press the space bar to enter the monitor, and automatically determines the baud rate: 300, 600, 1200, 2400, 4800, or 9600. The manual says it supports 110, but we could not get that to work.

9600 BAUD SERIAL
IMSAI MPU-B MONITOR    VERS 1.3
?▒

Commands

Refer to the IMSAI MPU-B Reference Manual for the monitor commands. Below is a preview showing how to display the first 256 bytes of the MPU-B firmware.

?D D800,D8FF

D800  3E 40 D3 F3 C3 10 D8 C3 3B DE C3 66 DE C3 EF D9  >@......;..f....
D810  31 E4 D0 21 80 00 22 FE D0 CD 7B D8 3D CA A7 D8  1..!.."...{.=...
D820  AF 32 F7 D0 21 FD FF 3E 56 BE C2 3C D8 23 3E 49  .2..!..>V..<.#>I
D830  BE C2 3C D8 3E 10 32 F7 D0 CD 00 F8 21 FA D0 22  ..<.>.2.....!.."
D840  F8 D0 3E AE D3 03 3E 27 D3 03 CD AE D8 21 A7 DF  ..>...>'.....!..
D850  CD 59 DE 31 E4 D0 21 56 D8 E5 CD B5 DE 3E 3F CD  .Y.1..!V.....>?.
D860  66 DE CD 3B DE 21 44 DF CD 8A DE CD E1 DD C8 CD  f..;.!D.........
D870  DB DE 06 01 E9 21 95 DF C3 68 D8 CD CA DC 21 F5  .....!...h....!.
D880  D0 3A FD E7 D6 44 C2 91 D8 3A FE E7 D6 49 CA 96  .:...D...:...I..
D890  D8 36 04 C3 EC DC CD 0C E0 36 02 CD EC DC F0 21  .6.......6.....!
D8A0  F5 D0 36 01 C3 EC DC 3E C0 D3 F3 C3 00 00 DB 14  ..6....>........
D8B0  21 C7 DF CD 59 DE 21 F7 D0 3E 10 A6 77 2B AF 77  !...Y.!..>..w+.w
D8C0  CD 53 D9 06 00 DB 12 B7 CA CC D8 04 CD 05 DE C2  .S..............
D8D0  20 D9 CD FD DD C2 31 D9 78 B7 CA CC D8 CD F5 DD   .....1.x.......
D8E0  CA CC D8 3C CA CC D8 06 00 CD F5 DD CA E9 D8 04  ...<............
D8F0  B7 CA E9 D8 21 1E DF 23 7E B7 CA B0 D8 B8 23 DA  ....!..#~.....#.

?▒

Control Port

The MPU-B manages its memory-mapped ROM, RAM, and Timers through the write-only port 0xF3:

  • Bit 6 (mask 0x40) controls whether the firmware ROM is mapped into the address space. Setting this bit to 0 (which is the default after a power-up or reset) maps the ROM to address 0x0000 through 0x07FF. Setting this bit to 1 unmaps the ROM and allows the CPU to access system memory for address 0x0000 through 0x07FF.
  • Bit 7 (mask 0x80) controls whether the firmware ROM, RAM, and the Timers are mapped into the address space. Setting this bit to 0 (which is the default after a power-up or reset) maps the ROM to address 0xD800 through 0xDFFF, the RAM to address 0xD000 through 0xD0FF, and the Timers to address 0xD100 through 0xD103. Setting this bit to 1 unmaps the ROM, RAM, and Timers and allows the CPU to access system memory for address 0xD000 through 0xD103, and address 0xD800 through 0xDFFF.

It is legal to map the ROM in both address ranges, one or the other, or not at all. The status of the control port is available on port 15 bits 6 and 7.

The control port waits for 3 additional machine cycles before any changing the memory map to allow a JMP or CALL instruction to execute. Interrupts must be disabled during this time and any INTA cycles would be counted. DMA cycles are not counted.


DYI Resources

If the information here was helpful to you, please consider making a donation to help us continue making content like this available.

Tips

We connected the SOD signal to J1-66 to drive a buzzer for sound.

Schematic

The best image of the schematic we could find is here. This one is for a rev 1 board. Unfortunately, we seem to have lost our hard copy somewhere over the past 40 years.

Manuals

Firmware

IC Datasheets

 


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