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IMSAI Standard Addresses

While most IMSAI boards have jumpers or DIP switches to let users set the base I/O port or memory mapped I/O address, the boards have what are considered to be standard addresses according to IMSAI CP/M, IMDOS, and many utility programs. The following section documents the standard addresses of most every IMSAI card ever made.

Standard Memory-Mapped Addresses

The IMSAI address space is 1MB, achieved by adding 4 upper address lines to the S-100 bus. The addresses here represent the default memory-mapped addresses and not RAM card addresses. For this reason, addresses are 5 hexadecimal digits with the upper digit separated by a space for readability. A 4-digit address indicates that the address decode does not take the 4 upper address lines into account, and will appear in all 64 kB banks.

Start End Product Can Disable Comments
0000 07FF MPU-B Control Port bit 6 The MPU-B begins execution of the firmware ROM here and almost immediately jumps to the D800 space after switching out the ROM here. This leaves this address range available for the system.
0000 EFFF System    
D000 D0FF MPU-B Control Port bit 7 The MPU-B on-board RAM.
D100 D103 MPU-B Control Port bit 7 The MPU-B Timers.
D104 D7FF MPU-B Control Port bit 7 Reserved. Do not use.
D800 DFFF MPU-B Control Port bit 7 The MPU-B firmware which starts at x 0000 and jumps here to complete the initialization.
F000 F7FF VIO No The VIO video refresh memory and command port when jumper M is not installed (default).
F800 FFFF VIO No The VIO firmware ROM when S1-5 is OFF jumper M is not installed (default).
F F000 F F7FF VIO No The VIO video refresh memory and command port when jumper M is installed.
F F800 F FFFF VIO No The VIO firmware ROM when S1-5 is OFF jumper M is installed. This is where the VIO was supposed to go with an IMM installed. To my knowledge, no software was ever released that used the IMM or the VIO this way.

Standard I/O Addresses

It should be noted that many IMSAI boards decode the address lines in a way that is considered to be non-standard in an IEEE-696 system. This behavior was enabled by the fact that the 8080, 8085, and Z80 processors would dublicate the I/O port address on the upper 8 address lines as well as the lower. For example, a reference to port 12 would output the 16-bit address 1212 on the address lines. Some boards (TODO: cite) would take advantage of this and decode the I/O port using the upper address lines.

Ports Product Comments
02−03 Many The standard character I/O for all IMSAI configurations. Applies to the MIO, MPU-B, SIO, and VIO boards, and the IMDOS operating system. Used in conjuction with port 03 for handshaking.
04−05 SIO The first SIO serial port.
12−13 SIO The second SIO serial port.
14−15 PIO The first PIO parallel port.
F3 MPU-B The MPU-B control port.
FD FIF The command port for the IFM/FIB board pair 8" SSSD floppy controller.
FE RAM-4A Controls the memory protect of each 1 KiB block in a 64 KiB system. See the RAM 4A documentation for details.
FF CP-A Reads the upper 8 address switches (A15 through A8) into bits 7 through 0; writes to the Programmed Output LEDs.

 


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